The invention relates to a method and apparatus for reducing data errors generated in a magneto-resistive random access memory (MRAM), and more particularly to a method of reducing switching currents in order to protect data integrity in an MRAM.
A recent development combines semiconductor technology with principles of magnetism to make magneto-resistive random access memory (MRAM) devices. In this approach, generation of electrical charge to indicate the presence of a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is replaced by the spin of an electron, obtained by means of using magnetic layers.
MRAMs include large numbers, of conductive lines positioned perpendicular to one another in different metal layers. The places where the perpendicular conductive lines intersect are known as the cross-points. At each cross-point, a magnetic stack is placed between the two perpendicular conductive lines.
Binary information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is stored as different alignments of the magnetic dipoles in the magnetic-stack. At the cross-point, an electrical current flowing through one of the conductive lines induces a magnetic field around the conductive line. In this way, the induced magnetic field can align the orientation of magnetic dipoles in the magnetic stack. A different current flowing through the other conductive line induces another magnetic field and can realign the polarity of the magnetic field in the magnetic stack. A current of sufficient strength flowing through one of the conductive lines is able to destroy the contents of the magnetic stacks coupled to it. However, currents flowing through both conductive lines are required to selectively program a particular magnetic stack.
The alignment of the magnetic dipoles in the magnetic stack changes the electrical resistance of the magnetic stack. For example, if a binary xe2x80x9c0xe2x80x9d is stored in the magnetic stack, the resistance of the magnetic stack will be different from the resistance of the same magnetic stack if a binary xe2x80x9c1xe2x80x9d is stored in it. It is the resistance of the magnetic stack that when detected, determines the logical value stored therein.
Because MRAM devices operate differently than other semiconductor memory devices, they introduce design and manufacturing challenges. One of these challenges has to do with the generation of xe2x80x9csoft-errorsxe2x80x9d. A xe2x80x9csoft-errorxe2x80x9d is a failure that only corrupts the data, while not affecting the circuit itself.
There are a number of causes associated with the generation of xe2x80x9csoft-errorsxe2x80x9d. For example, xe2x80x9csoft-errorsxe2x80x9d may be generated by unintended realignment of magnetic dipoles. Such reversals can ultimately affect the resistance of the magnetic stack and the binary value stored in the magnetic stack. As the operating voltages and size of microelectronic devices continue to shrink to satisfy the demand for low power, high density semiconductor devices are being used more widely. However, high density semiconductor devices create higher thermal characteristics that lead to such realignments.
A second, closely associated, challenge affecting data integrity occurs during writing of data streams in an MRAM. It is well known to those skilled in the art that the magnetic selectivity of an ideal magnetic memory cell occurs along a hard magnetic axis, often representing the word line field, and an easy magnetic axis, which represents the bit line field. Since MRAM storage cells are placed at cross-points between word lines and bit lines, and writing is performed by locally elevated magnetic fields, writing to individual memory cells without also writing to adjacent or other non-intended cells can be sometimes problematic. This is because, typically, writing a memory cell involves passing electrical currents simultaneously through the bit line and the word line at the cross-point where the selected cell is located. The selected cell is subjected to a magnetic field which is the vector sum of the magnetic fields created by the word and bit line currents. All other cells that share the same bit line or the same word line as the selected cell will be half-selected, and will thus be subjected to either the bit line magnetic field or the word line magnetic field. As known in the art, the vector sum of the magnetic fields of the word line and the bit line is only slightly larger than the individual magnetic fields of the word line or the bit line, such that the selectivity of a selected cell over half-selected cells is poor, especially when the non-uniform switching characteristics of the cells are considered. The difference between the magnetic field strength at a selected cell and that of a half-selected cell is known as write select margin.
Variations in the shapes or sizes of cells within an MRAM can give rise to variations in magnetic thresholds of the cells which are so large that it may become impossible to write a selected cell without unintentionally reversing the stored states in some of the half-selected cells, thus placing the reliability and validity of the stored data in question. There may also be environmental or other factors, such as temperature and processing variations, that adversely affect the write select margin. Additionally, the spontaneous switching of states in a cell, when it is subjected to repeated reversals of the magnetic field that are lower the nominal switching field narrows the acceptable write select margin further, making greater selectivity of individual cells imperative. An illustrative example is presented in FIG. 1.
FIG. 1 is a prior art diagram illustrating the magnetic selectivity of an MRAM cell. Assume that the currents of the word line and the bit line crossing at a particular MRAM cell generate fields along the hard magnetic axis at point (110), and along the easy magnetic axis at point (130), respectively. The field (Hx, Hy) required to switch the magnetic state of the cell must equal or exceed the boundary (100). This boundary curve (100), known by those skilled in the art as a switching asteroid, satisfies the relation Hx⅔+Hy⅔=Hk⅔, where Hx is the hard axis field, Hy is the easy axis field, and Hk is an anisotropy field. A selected MRAM is subjected to magnetic fields outside the boundary (100) of the switching asteroid, e.g., corresponding to point (120)) which are large enough to write the MRAM cell to a state that aligns with the easy axis field direction. The state of a half-selected cell does not change, since the magnetic fields acting on it, (that is, the fields corresponding to points, (110) and (130) remain within the boundary (100) of the switching asteroid.
Other than these challenges affecting data integrity, there are numerous other concerns which may have adverse effects on data including operating conditions such as temperature and electrical charge. Regardless of the cause of data integrity problems, however, new systems and methods are needed to eliminate, or at least minimize their effects on MRAM operation. The present invention provides a system and method for resolution of errors affecting data integrity that is easy to implement without being cost prohibitive.
It should be noted, in the description of the invention to follow, that while, for illustrative purposes, the first two challenges discussed above are used throughout to highlight the benefits of the present invention, in particular as to handling unintended reversals, the present invention can be applied to other situations where data errors are to be minimized to preserve data integrity.
The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to a method provided by the invention, data bits and error correction code (ECC) check bits are stored into a storage area. The data bits and the ECC check bits are then read out and errors in the data bits are checked and corrected with the ECC check bits. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area. In an embodiment of the invention, the stored data bits and ECC check bits are refreshed based on certain other criteria, to further increase tolerance of the MRAM to errors.